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10200 LABs ALTERA FPGA Chip

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10200 LABs ALTERA FPGA Chip

Name: 10200 LABs ALTERA FPGA Chip
Brand: Intel / Altera
Price: 15000 USD

Brand Name : Intel / Altera

Model Number : EP3SE260F1152I3N

Certification : Lead free / RoHS Compliant

MOQ : 1 pcs

Price : USD 15000-20000 pcs

Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card

Supply Ability : 72 pcs

Delivery Time : 3-5 Day

Packaging Details : International Standard Packaging

Category : IC FPGA

Condition : Original 100%,Brand New and Original,New

Series : Stratix III Enhanced

Number of Logic Array Blocks - LABs : 10200

Number of I/Os : 744 I/O

Package / Case : FBGA-1152

Operating Supply Voltage : 1.2 V to 3.3 V

Embedded Block RAM - EBR : 1594 kbit

Service : BOM Kitting

Lead time : In Stock,contact us

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EP3SE260F1152I3N ALTERA FPGA Chip FBGA-1152 Stratix III Enhanced

Product Attribute	Attribute Value
Manufacturer:	Intel
Product Category:	FPGA - Field Programmable Gate Array
Product:	Stratix III Enhanced
Number of Logic Elements:	255000
Number of Logic Array Blocks - LABs:	10200
Number of I/Os:	744 I/O
Operating Supply Voltage:	1.2 V to 3.3 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-1152
Packaging:	Tray
Series:	Stratix III
Brand:	Intel / Altera
Embedded Block RAM - EBR:	1594 kbit
Moisture Sensitive:	Yes
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	24
Subcategory:	Programmable Logic ICs
Total Memory:	16282 kbit
Tradename:	Stratix
Part # Aliases:	972418

Stratix III devices offer the following features:

■ 48,000 to 338,000 equivalent logic elements (LEs) ( refer to Table 1–1)
■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
■ High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity
■ Programmable Power Technology, which minimizes power while maximizing device performance
■ Selectable Core Voltage, available in low-voltage devices (L ordering code suffix), enables selection of lowest power or highest performance operation
■ Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
■ Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis, and dynamic phase shifting
■ Memory interface support with dedicated DQS logic on all I/O banks
■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

10200 LABs ALTERA FPGA Chip

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